A research team consisting of Yoichiro Kurita, Distinguished Professor at the Future Intersection Science and Technology Research Laboratory of the Institute of Innovation, Tokyo Institute of Technology (Tokyo Institute of Technology), and a collaborative research company developed the technology using a technology called “Pillar-Suspended Bridge (PSB).” Meet the requirements for broadband chip-to-chip communication and scalable chiplet integration, which is required for large-scale chiplet integration in the future, with minimal configuration and manufacturing processes.
It has a silicon bridge interconnect structure that enables broadband communication between chips through a fine “MicroPillar” and uses a manufacturing process called “All Chip-last”. This structure and process provide the requirements for chiplet integration in the simplest form. The technology is expected to accelerate the evolution of future semiconductor integrated circuit system technology, replacing the expected slowdown in miniaturization.
This research was conducted jointly with Aoi Electronics Co., Ltd. and four other companies ahead of the Chiplet Integration Platform Alliance (described later), which will be launched on October 1. Detailed results will be presented at the IMAPS 2022 International Conference in Boston, USA on October 3.
Since its invention in the mid-20th century, semiconductor integrated circuits have been the driving force behind the world’s digital transformation with Moore’s Law, improving performance, reducing power consumption, and reducing costs through device miniaturization and increased integration. However, in recent years, the size of semiconductor circuits has been miniaturized to several nanometers. Industry now recognizes the demise of this law due to physical constraints imposed by the size of the atoms that make up semiconductors.
Meanwhile, chiplet integration technology (Figure 1) is gaining attention as a new evolutionary path to expand integration and improve performance/reduce power consumption in lieu of miniaturization. This includes assembling major systems from collections of integrated circuit chips that are more tightly coupled than traditional semiconductor packaging techniques. This goes beyond the physical/manufacturing technology dimensions of semiconductor wafers and chips, integrating different functions and structures at scale. This makes it possible to deliver improved performance through heterogeneous integration and integration scalability, which is not possible with conventional semiconductor integrated circuit technologies.
Integration technologies using silicon interposers and polymer-based RDL (Redistribution Layer) interposers (also known as RDL-first/Chip-last Fan-Out) have been developed and implemented as platform technologies for chiplet integration, but large Scale integration is limited according to wafer size and fabrication technology. Meanwhile, a technology using locally arranged high-density wiring chips, called silicon bridges, is being developed to enable large-scale integration. However, the complexity of the structures and fabrication processes and the high fabrication precision required to increase the level of integration present challenges.
The researchers designed the Pillar-Suspended Bridge (PSB) technology as a chiplet integration structure/process with the simplest scheme and produced a proof-of-concept prototype to demonstrate its feasibility. Figures 1 and 2 show a PSB bridge structure. Only a pillar of metal called “MicroPillar” is inserted at the connection between the chiplet and the silicon bridge. The chiplets are encapsulated with a molding resin along with the bridges and connected to external electrodes by “tall posts” that pass through the mold on the silicon bridge side.
This structure can improve inter-chip connection density and electrical performance by minimizing chiplet/bridge interconnect elements, and can improve high-frequency characteristics and heat dissipation performance of external connection wiring. Another advantage of it is that the type of bridge line can be selected, there is no yield problem when scaling up the integration (Known Good Bridge), the size of the integrated module and the manufacturing unit can be extended to large panels.
This structure is created by (1) high bonding accuracy and reduced “chip movement” (the phenomenon of chip movement during die sealing) during manufacturing in the All Chip-last process and (2) a bonding process with matching linearity Expansion (Coefficient of Thermal Expansion: CTE).
Although the miniaturization of semiconductor integrated circuits is expected to slow down due to Moore’s Law, chiplet integration technology may be a new evolutionary path to improve system performance. This platform technology is expected to have a huge impact on human society in the long run, accompanied by the emergence of huge industries. This technology and its component technologies and applications are expected to drive these trends.
The researchers plan to increase interconnect density and expand integration, develop high-performance bridging wire technology and global routing integration technology, verify reliability, and validate system applications.
In addition, they will also establish the Chiplet Integration Platform Alliance, which aims to conduct research and development in the value chain from manufacturing technology and component technology to application and its industrialization, targeting the entire chiplet integration platform technology including this study.
No Space Wasting: Embedding Capacitors in Interposers for Increased Miniaturization
Provided by Tokyo Institute of Technology
Citation: Find the chiplet integration technology with the simple scheme (2022, October 7) Retrieved on October 7, 2022 https://techxplore.com/news/2022-10-chiplet-technology-simplest-scheme.html
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